1. Field of the Invention
The present invention relates to a high speed transmission system, such as a wideband digital cross-connect system (WDCS) and a broadband digital cross-connect system (BDCS), etc., and in particular to an apparatus and a method for transmitting data between transmission systems that each uses a clock source having a phase different from the other.
2. Background of the Related Art
A digital cross-connect system (DCS) is a high speed transmission system. The DCS receives a digital signal level N (DS-N) as an asynchronous signal and a synchronous transport module level N (STM-N) as a synchronous signal, and performs functions such as circuit distribution, branch, performance monitoring, test connection and network management.
The DCS includes a wideband digital cross-connect system (WDCS) and a broadband digital cross-connect system(BDCS).
The WDCS performs a cross-connect function of DS1, DS1E, DS3 and STM-N signals, and performs circuit distribution by wavelengths in a TU3/TU12 hierarchy. The BDCS performs a cross-connect function of DS3 and STM-N signals, and cross-connects a signal inputted from an AU3/AU4 hierarchy with a channel by using non-blocking digital switching according to an electronic control without performing a digital/analog conversion. Simultaneously the BDCS performs functions of a PCM terminal apparatus, a multiplexer, and an optical transmission apparatus and receives a broadband service circuit used for a broadband intergrated services digital network (B-ISDN).
The WDCS and the BDCS each uses a system clock having a phase different from the other. Although each transmission system uses a system clock different from the other, data transmission is required between the transmission systems.
Accordingly, a dual port RAM (DPRAM) is largely used to process data between transmission systems using dissimilar system clocks. Generally, the DPRAM includes an input port and an output port and can input/output data through the input/output ports.
FIG. 1 is a block diagram illustrating a construction of a related art data transmission apparatus between transmission systems using dissimilar phase clocks.
As depicted in FIG. 1, the related art data transmission apparatus between the transmission systems using the dissimilar clocks includes a receiving unit 10 for processing reception data according to a first system clock (SysClk_A) based on a clock source of a first system and a write address generating unit 20 for generating a write address according to the first system clock. The apparatus further includes a read address generating unit 30 for generating a read address according to a second system clock (SysClk_B) based on a clock source of a second system and a transmitting unit 50 for processing transmission data according to the second system clock. Finally, a DPRAM 40 is provided for processing data between the receiving unit 10 and the transmitting unit 50 according to the write address and the read address.
An operation of the related art data transmission apparatus between the transmission systems using the dissimilar clocks as depicted in FIG. 1 is next described. In this example, data is transmitted from the first system to the second system will be described.
When data is transmitted from the first system to the receiving unit 10 of the second system, the write address generating unit 20 outputs a write address (W_ADD), a write clock (WCLK), and a write enable signal (WREN) to the DPRAM 40 according to the first system clock (SysClk_A).
The receiving unit 10, which is operated according to the first system clock, stores the received data in a memory through the input port of the DPRAM 40 according to the write address (W_ADD).
In the meantime, the read address generating unit 30 outputs a read address (R_ADD), a read clock (RCLK), and a read enable signal (RDEN) to the DPRAM 40 according to the second system clock (SysClk_B).
The transmitting unit 50, which is operated according to the second system clock (SysClk_B), fetches data from the read address through the output port of the DPRAM 40 and transmits it to the second system.
Data transmission from the second system to the first system is performed by the same method as that for transmitting data from the first system to the second system. Accordingly, an explanation related to that process will be omitted.
By using the DPRAM 40 to perform both input and output functions, the related art apparatus for transmitting data between the transmission systems using the dissimilar phase clocks can transmit/receive data between the first system operating according to the first system clock and the second system operating according to the second system clock.
However, the related data transmission apparatus between the transmission systems using the dissimilar phase clocks has various problems. For example, because a write address and a read address applied to the DPRAM may be simultaneously generated at a certain time “t”, the two addresses collide with each other. In that case, due to the collision of the write address and the read address, data write and output functions may not be performed normally, and data transmission capacity may be lowered.
The above references are incorporated by reference herein where appropriate for appropriate teachings of additional or alternative details, features and/or technical background.